1. Field
The various circuit embodiments described herein relate in general to memory architectures and methods for accessing same, and more specifically to methods and circuit architectures for enabling substantially simultaneous read and write functions in a static random access memory (SRAM).
2. Background
Accessing a memory with read and write functions in a single clock cycle has been a continuous customer need. In the past, this has been accomplished using sequential rising and falling edges of the clock in a clock cycle. This is referred to as “two-port functionality.” This enables twice the cycle time of a single-port memory to be achieved. However, timing mismatches and lower operating voltages that are being used with ever-increasingly smaller topologies limit the performance of the two-port functionality mode of operation.
An asynchronous feature has been employed that allows two-port functionality in a given clock cycle by making the asynchronous internal memory signal available. An example of this can be seen in memories that are included in embedded processor circuitry, such as compilers constructed around high performance RAM structures. This has helped overcome at least some of the performance limitations introduced by the dual-edge usage. However, the asynchronous feature clocks the memory at the highest speed available irrespective of the external clock. Hence, the memory is prone to timing mismatches. This often resulting in yield loss in production of the circuits.
An eight transistor (8T) bit cell has been developed in 28 nm technology that has addressed at least some of the needs of robust, high performance, two-port and single-port RAMs. The 8T bit cell considered the functionality of both the single port and two port memory topologies. This provided opportunity to design a two port architecture having the functionality of a read operation followed by a write operation. The two-port architecture helped to improve the performance limitations, but it still unable to achieve simultaneous read and write operations at the same bit cell. It additionally has potential errors that can lead to functional failures when accessing the same row in a memory array.
An electrical schematic diagram of a previously proposed 8T bit cell 10 is shown in FIG. 1, to which reference is now made. It is understood, of course, that the 8T bit cell 10 is only one of a number of bit cells of a memory array. The bit cells are arranged in rows and columns with each bit cell being individually addressable with appropriate row and column addressing signals and associated logic circuitry. Typically, the bit cells are arranged so that a predetermined number of bit cells can be concurrently addressed, for example, to store and deliver information in predetermined quantities, such as bytes, words, or the like.
The 8T bit cell 10 uses six transistors for a write operation and two transistors for a high performance read operation. The 8T cell has cross coupled inverters 12 and 14 that are respectively connected to write bit lines 16 and 18 (WBIT and WBIT) by access or pass-gate transistors 20 and 22. The inverter 12 has a PMOS transistor 24 and an NMOS transistor 26 connected between VCC and ground, and the inverter 14 has a PMOS transistor and an NMOS transistor 30, also connected between VCC and ground. The gates of the PMOS transistor 24 and the NMOS transistor 26 of the inverter 12 are connected between the PMOS transistor 24 and an NMOS transistor 26 of the inverter 14. Likewise, the gates of the PMOS transistor 28 and the NMOS transistor 30 of the inverter 14 are connected between the PMOS transistor 24 and an NMOS transistor 26 of the inverter 14. The circuitry encircled by the dashed circle 32 is essentially a 6T bit cell (except that the lines designated as write bit lines 16 and 18 would also be used for a read function in a 6T mode of operation). In the 8T bit cell illustrated a stack 37 of NMOS transistors 34 and 36 is connected between the node between the PMOS transistor 24 and an NMOS transistor 26 of the inverter 14 and a read bit output line 38 (RBIT).
In operation, a read address signal (AR/EZR) is applied to a read address line 40 and synchronized with a clock signal on line 42 in a read address latch/clock circuit 44. A read control signal is developed on a read word line 46 (RWL). Similarly, a write address signal (AW/EZW) is applied to a write address line 48 and synchronized with the clock signal on line 42 in a write address latch/clock circuit 50. A write control signal is developed on write line 52 (WWL).
Data to be written to the memory cell 10 is applied from data input line 54 via data latch/decoding logic circuit 56 to the write bit lines 16 and 18. The output to be read from the circuit is sensed on line 38 by sensing logic and output driver circuitry 58, and delivered on output line 60.
The 8T bit cell 10 performs read and write operations in the same architectural context as a topology in which the two port operation can be performed. In the positive phase of clock, parallel write and read word lines can be activated based on the value of the read address (AW/EZR) and write address (AR/EZR) signals on respective read address line 40 and write address line 52. Thus, the bit cell in the array having both word lines on can be selectively addressed, allowing data from the data latch/decoding logic circuit 56 to be written into the bit cell 10, and allowing the internal value of the bit cell 10 to be read through the single ended sensing mechanism provided by the NMOS transistors 34 and 36 in the transistor stack 37. The periphery logic circuits, including the read address latch/clock circuit 44, the write address latch/clock circuit 50, the data latch/decoding logic 56, and the sensing logic and output driver 60 are designed so that the bit cell 10 can perform parallel operations, enabling the bit cell 10 to provide high-performance read and write operations.
In reading and writing to an 8T cell of the type described, a number of scenarios exist. When the read and write addresses are different, the read word line and the write word line index different bit cells in the memory array. In this scenario, parallel read and write operations can be concurrently performed successfully. However, when the read and write addresses are same, both the read and write word lines are indexed to the same memory bit cell. With this architecture, a successful read operation cannot be guaranteed. Finally, when the read and write addresses index the same row but a different column in the array, a potential functional failure occurs.
In the case where the read and write addresses index the same memory bit cells, two possibilities exist. First, if the write operation to the bit cell occurs before the read operation, the new data can be read from the bit cell. Second, if the read operation occurs before the new data is written to it, old data will be read from the bit cell. This particular sequencing is unpredictable. Moreover, the unpredictability can worsen due to mismatches of the transistors in the bit cell and to sensitivities to low operating voltages.
Additionally, potential functionality failure or high leakage currents may exist when accessing the same row of bit cells. If both the read word line 46 and the write word line 52 for the same memory row are on and the internal voltage of ‘Q’ at node 31 is at a low level, i.e., Q=“0”, the write bit line, WBIT, 18 starts discharging through the NMOS transistors 22 and 30. This causes the internal voltage at node 31 to increase to a certain level, for example, about 400 mv. This increase in the internal voltage can be seen as high or partial high by some transistors, particularly the read transistor 34. The false read current discharges the voltage on the read bit line 38 to an intermediate value between VDD and 0.6 VDD. This can flip the stages in the sensing logic and output driver circuitry 60 and cause a false read operation. In addition, the discharge of the read bit line 38 to an intermediate value can cause a large IDDQ current to the following stages. This can be aggravated with the word length of the memory, since the read and write bit lines span the entire word length.
The clocking functions that have been previously employed are illustrated in FIGS. 2 and 3, to which reference is now additionally made. The memory bit cell (or row of bit cells) 10 receive the read and write addresses AR/EZR and AW/EZW on input lines 40 and 48, as described above. The clock signal is received on line 42. These signals are applied to the internal read address latch/clock circuit 44 and write address latch/clock circuit 50, which provide internal clock signals on the write internal clock line WWL 52 and read internal clock line RWL 46. The waveforms of various clocking signals are shown in FIG. 3. The external clock signal 70 has a transition from low to high 72 for a first time period 74. The clock signal then transitions 76 back to a low state for a second time period 78 and cycle is repeated.
Meanwhile, the read address latch/clock circuit 44 and write address latch/clock circuit 50 cause the read word line 46 and write word line 52 to change states when the bit cell is addressed by the read and write address signals on lines 40 and 48. The state changes of the read word line 46 and write word line 52 are shown by waveforms 80 and 82, respectively, in FIG. 3. As shown, the clock waveforms of the read word line 46 and write word line 52 substantially follow the waveform of the external clock signal 70, having a high state during the first period 74 and a low state during the second period 78. During the first time period 74 when both the read and write signals are high, respective read and write operations are concurrently performed in the bit cell 10. Subsequently, during the second period 78 when the read and write signals are low, the read and write word lines are precharged for the next read and write operations.
It can be seen that the concurrent operations performed using this timing scenario result in the issues described in greater detail above. These issues have been addressed in the past by restricting simultaneous read and write operations in the same bit cell.
What is needed is a memory architecture and method for operating same that can achieve high performance and two-port functionality, that has the ability to perform read and write operations on the same bit cell during a single clock cycle, and that has a robust architecture that can reduce mismatch and allow low voltage operations.